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DUAL CMOS SyncFIFOTM
Integrated Device Technology, Inc.
IDT72801 IDT72811 IDT72821 IDT72831 IDT72841
FEATURES:
* The 72801 is equivalent to two 72201 256 x 9 FIFOs * The 72811 is equivalent to two 72211 512 x 9 FIFOs * The 72821 is equivalent to two 72221 1024 x 9 FIFOs * The 72831 is equivalent to two 72231 2048 x 9 FIFOs * The 72841 is equivalent to two 72241 4096 x 9 FIFOs * Offers optimal combination of large capacity, high speed, design flexibility and small footprint * Ideal for prioritization, bidirectional, and width expansion applications * 15 ns read/write cycle time FOR THE 72801/72811 * 20 ns read/write cycle time FOR THE 72821/72831/72841 * Separate control lines and data lines for each FIFO * Separate empty, full, programmable almost-empty and almost-full flags for each FIFO * Enable puts output data lines in high-impedance state * Space-saving 64-pin Thin Quad Flat Pack (TQFP) * Industrial temperature range (-40OC to +85OC) is available, tested to military electrical specifications
DESCRIPTION:
72801/72811/72821/72831/72841 are dual synchronous
(clocked) FIFOs. The device is functionally equivalent to two 72201/72211/72221/72231/72241 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs (designated FIFO A and FIFO B) contained in the 72801/72811/72821/72831/72841 has a 9bit input data port (DA0 - DA8), DB0 - DB8) and a 9-bit output data port (QA0 - QA8, QB0 - QB8). Each input port is controlled by a free-running clock(WCLKA, WCLKB), and two write enable pins (WENA1, WENA2, WENB1, WENB2). Data is written into each of the two arrays on every rising clock edge of the write clock (WCLKA WCLKB) when the appropriate write enable pins are asserted. The output port of each FIFO bank is controlled by its associated clock pin (RCLKA, RCLKB) and two read enable pins (RENA1, RENA2, RENB1, RENB2). The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. An output enable pin (OEA, OEB) is provided on the read port of each FIFO for three-state output control . Each of the two FIFOs has two fixed flags, empty (EFA, EFB) and full (FFA, FFB). Two programmable flags, almost-empty (PAEA, PAEB) and almost-full (PAFA, PAFB), are provided for
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
GND QB8 QB7 QB6 QB5 QB4 QB3 QB2 QB1
QA0
FFA EFA OEA RENA2 RCLKA RENA1
PIN CONFIGURATION
QA1 QA2 QA3 QA4 QA5 QA6 QA7 QA8 VCC WENA2/LDA WCLKA
WENA1 RSA
DA8 DA7 DA6
PAFA PAEA WENB2/LDB WCLKB WENB1 RSB
DA5 DA4 DA3 DA2 DA1 DA0
DB8 DB7 DB6 DB5
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
PN64-1
TQFP, TOP VIEW
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
FFB EFB OEB RENB2 RCLKB RENB1
GND VCC DB0 DB1 DB2 DB3 DB4
QB0
PAEB PAFB
3034 drw 01
SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
(c)1996 Integrated Device Technology, Inc For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
NOVEMBER 1996
DSC-3034/1
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72801/72811/72821/72831/72841 DUAL CMOS SyncFIFOTM 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
COMMERCIAL TEMPERATURE
each FIFO bank to improve memory utilization. If not programmed, the programmable flags default to empty+7 for PAEA and PAEB, and full-7 for PAFA and PAFB. The 72801/72811/72821/72831/72841 architecture lends itself to many flexible configurations such as: * 2-level priority data buffering * Bidirectional operation * Width expansion * Depth expansion This FIFO is fabricated using IDTs high-performance submicron CMOS technology.
FUNCTIONAL BLOCK DIAGRAM
WCLKA DA0 - DA8 WENA2 WENB2 WCLKB DB0 - DB8
INPUT REGISTER
OFFSET REGISTER
INPUT REGISTER
OFFSET REGISTER
WRITE CONTROL LOGIC RAM ARRAY 256 x 9, 512 x 9, 1024 x 9, 2048 x 9, 4096 x 9
FLAG LOGIC
WRITE CONTROL LOGIC RAM ARRAY 256 x 9, 512 x 9, 1024 x 9, 2048 x 9, 4096 x 9
FLAG LOGIC
WRITE POINTER
READ POINTER
WRITE POINTER
READ POINTER
READ CONTROL LOGIC
READ CONTROL LOGIC
OUTPUT REGISTER RESET LOGIC RESET LOGIC
OUTPUT REGISTER
QA0 - QA8
RCLKA QB0 - QB8
RCLKB
3034 drw 01A
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72801/72811/72821/72831/72841 DUAL CMOS SyncFIFOTM 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
COMMERCIAL TEMPERATURE
PIN DESCRIPTIONS
The 72801/72811/72821/72831/72841s two FIFOs, referred to as FIFO A and FIFO B, are identical in every respect. The following description defines the input and output signals for FIFO A. The corresponding signal names for FIFO B are provided in parentheses.
Symbol
DA0-DA8 DB0-DB8
Name I/O
A Data Inputs B Data Inputs Reset I I I
Description
9-bit data inputs to RAM array A. 9-bit data inputs to RAM array B. When RSA (RSB) is set LOW, the associated internal read and write pointers of array A (B) are set to the first location; FFA (FFB) and PAFA (PAFB) go HIGH, and PAEA (PAEB) and EFA (EFB) go LOW. After power-up, a reset of both FIFOs A and B is required before an initial WRITE. Data is written into the FIFO A (B) on a LOW-to-HIGH transition of WCLKA (WCLKB) when the write enable(s) are asserted. If FIFO A (B) is configured to have programmable flags, WENA1 (WENB1) is the only write enable pin that can be used. When WENA1 (WENB1) is LOW, data A (B) is written into the FIFO on every LOW-to-HIGH transition WCLKA (WCLKB). If the FIFO is configured to have two write enables, WENA1 (WENB1) must be LOW and WENA2 (WENB2) must be HIGH to write data into the FIFO. Data will not be written into the FIFO if FFA (FFB) is LOW. FIFO A (B) is configured at reset to have either two write enables or programmable flags. If LDA (LDB) is HIGH at reset, this pin operates as a second write enable. If WENA2/LDA (WENB2/LDB) is LOW at reset this pin operates as a control to load and read the program mable flag offsets for its respective array. If the FIFO is configured to have two write enables, WENA1 (WENB1) must be LOW and WENA2 (WENB2) must be HIGH to write data into FIFO A (B). Data will not be written into FIFO A (B) if FFA (FFB) is LOW. If the FIFO is configured to have programmable flags, LDA(LDB) is held LOW to write or read the programmable flag offsets. 9-bit data outputs from RAM array A. 9-bit data outputs from RAM array B. Data is read from FIFO A (B) on a LOW-to-HIGH transition of RCLKA (RCLKB) when RENA1 (RENB1) and RENA2 (RENB2) are asserted.
RSA, RSB
WCLKA WCLKB
Write Clock Write Enable 1
I I
WENA1 WENB1
WENA2/LDA WENB2/LDB
Write Enable 2/ Load
I
QA0-QA8 QB0-QB8 RCLKA RCLKB
A Data Outputs O B Data Outputs O Read Clock Read Enable 1 I I
RENA1 RENB1 RENA2 RENB2 OEA OEB EFA EFB PAEA PAEB PAFA PAFB FFA FFB
VCC GND
When RENA1 (RENB1) and RENA2 (RENB2) are LOW, data is read from FIFO A (B) on every LOW-to-HIGH transition of RCLKA (RCLKB). Data will not be read from Array A (B) if EFA (EFB) is LOW. When RENA1 (RENB1) and RENA2 (RENB2) are LOW, data is read from the FIFO A (B) on every LOW-to-HIGH transition of RCLKA (RCLKB). Data will not be read from array A (B) if the EFA (EFB) is LOW.
Read Enable 2
I
Output Enable Empty Flag
I O
When OEA (OEB) is LOW, outputs DA0-DA8 (DB0-DB8) are active. If OEA (OEB) is HIGH, the outputs DA0-DA8 (DB0-DB8) will be in a high-impedance state. When EFA (EFB) is LOW, FIFO A (B) is empty and further data reads from the output are inhibited. When EFA (EFB) is HIGH, FIFO A (B) is not empty. EFA (EFB) is synchronized to RCLKA (RCLKB). When PAEA (PAEB) is LOW, FIFO A (B) is almost empty based on the offset programmed into the appropriate offset register. The default offset at reset is Empty+7. PAEA (PAEB) is synchro nized to RCLKA (RCLKB). When PAFA (PAFB) is LOW, FIFO A (B) is almost full based on the offset programmed into the appropriate offset register. The default offset at reset is Full-7. PAFA (PAFB) is synchronized to WCLKA (WCLKB). When FFA (FFB) is LOW, FIFO A (B) is full and further data writes into the input are inhibited. When FFA (FFB) is HIGH, FIFO A (B) is not full. FFA (FFB) is synchronized to WCLKA (WCLKB). +5V power supply pin. 0V ground pin.
3034 tbl 01
Programmable Almost-Empty Flag
O
Programmable O Almost-Full Flag Full Flag O
Power Ground
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72801/72811/72821/72831/72841 DUAL CMOS SyncFIFOTM 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
COMMERCIAL TEMPERATURE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Rating Terminal Voltage with VTERM Respect to GND Operating Temperature TA Temperature Under Bias TBIAS TSTG IOUT Storage Temperature DC Output Current Commercial -0.5 to +7.0 0 to +70 -55 to +125 -55 to +125 50 Unit V C C C mA
3034 tbl 02
RECOMMENDED OPERATING CONDITIONS
Symbol VCC GND VIH VIL Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Min. 4.5 0 2.0 -- Typ. 5.0 0 -- -- Max. 5.5 0 -- 0.8 Unit V V V V
3034 tbl 03
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE (TA = +25C, f = 1.0MHz)
Symbol CIN
(2) (1,2)
Parameter Input Capacitance Output Capacitance
Conditions VIN = 0V VOUT = 0V
Max. 10 10
Unit pF pF
3034 tbl 04
COUT
NOTE: 1. With output deselected (OEA, OEB = HIGH).
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V 10%, TA = 0C to +70C)
IDT72801 IDT72811 Commercial tCLK = 15, 20, 25, 35ns Typ. -- -- -- -- --
Symbol ILI
(1)
Parameter Input Leakage Current (Any Input) Output Leakage Current Output Logic "1" Voltage, IOH = -2 mA Output Logic "0" Voltage, IOL = 8 mA Active Power Supply Current
Min. -1 -10 2.4 -- --
Max. -1 10 -- 0.4 270
Unit A A V V mA
3034 tbl 05
ILO(2) VOH VOL ICC(3)
IDT72821 IDT72831 IDT72841 Commercial tCLK = 20, 25, 35 ns Typ. -- -- -- -- --
Symbol ILI
(1)
Parameter Input Leakage Current (Any Input) Output Leakage Current Output Logic "1" Voltage, IOH = -2 mA Output Logic "0" Voltage, IOL = 8 mA Active Power Supply Current
Min. -1 -10 2.4 -- --
Max. -1 10 -- 0.4 300
Unit A A V V mA
3034 tbl 06
ILO(2) VOH VOL ICC(3)
NOTES: 1. Measurements with 0.4 VIN VCC. 2. OEA, OEB VIH, 0.4 VOUT VCC. 3. Measurements are made with outputs open. Tested at fCLK = 20MHz. Icc limits applicable when using both banks of FIFOs simultaneously.
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72801/72811/72821/72831/72841 DUAL CMOS SyncFIFOTM 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
COMMERCIAL TEMPERATURE
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V 10%, TA = 0C to +70C)
Commercial IDT72801L12 IDT72801L15 IDT72801L20 IDT72801L25 IDT72801L35 IDT72811L12 IDT72811L15 IDT72811L20 IDT72811L25 IDT72811L35 IDT72821L12 IDT72821L15 IDT72821L20 IDT72821L25 IDT72821L35 IDT72831L12 IDT72831L15 IDT72831L20 IDT72831L25 IDT72831L35 IDT72841L12 IDT72841L15 IDT72841L20 IDT72841L25 IDT72841L35 Symbol fS tA tCLK tCLKH tCLKL tDS tDH tENS tENH tRS tRSS tRSR tRSF tOLZ tOE tOHZ tWFF tREF tPAF tPAE Parameter Clock Cycle Frequency Data Access Time Clock Cycle Time Clock High Time Clock Low Time Data Set-up Time Data Hold Time Enable Set-up Time Enable Hold Time Reset Pulse Width(1) Reset Set-up Time Reset Recovery Time Reset to Flag Time and Output Time Output Enable to Output in Low-Z(2) Output Enable to Output Valid Output Enable to Output in High-Z(2) Write Clock to Full Flag Read Clock to Empty Flag Write Clock to Programmable Almost-Full Flag Read Clock to Programmable Almost-Empty Flag tSKEW1 Skew Time Between Read Clock and Write Clock for Empty Flag and Full Flag tSKEW2 Skew Time Between Read Clock and Write Clock for Programmable Almost-Empty Flag and Programmable Almost-Full Flag
NOTES: 1. Pulse widths less than minimum values are not allowed. 2. Values guaranteed by design, not currently tested.
Min. Max. -- 2 12 5 5 3 0 3 0 12 12 12 -- 0 3 3 -- -- -- -- 5 83.3 8 -- -- -- -- -- -- -- -- -- -- 12 -- 7 7 8 8 8 8 --
Min. Max. -- 2 15 6 6 4 1 4 1 15 15 15 -- 0 3 3 -- -- -- -- 6 66.7 10 -- -- -- -- -- -- -- -- -- -- 15 -- 8 8 10 10 10 10 --
Min. Max. -- 2 20 8 8 5 1 5 1 20 20 20 -- 0 3 3 -- -- -- -- 8 50 12 -- -- -- -- -- -- -- -- -- -- 20 -- 10 10 12 12 12 12 --
Min. Max. -- 3 25 10 10 6 1 6 1 25 25 25 -- 0 3 3 -- -- -- -- 10 40 15 -- -- -- -- -- -- -- -- -- -- 25 -- 13 13 15 15 15 15 --
Min. Max. Unit -- 3 35 14 14 8 2 8 2 35 35 35 -- 0 3 3 -- -- -- -- 12 28.6 MHz 20 -- -- -- -- -- -- -- -- -- -- 35 -- 15 15 20 20 20 20 -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
22
--
28
--
35
--
40
--
42
--
ns
3034 tbl 07
5V
1.1K
AC TEST CONDITIONS
In Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 3ns 1.5V 1.5V See Figure 1
3034 tbl 08
D.U.T. 680 30pF*
3034 drw 03
or equivalent circuit Figure 1. Output Load *Includes jig and scope capacitances.
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72801/72811/72821/72831/72841 DUAL CMOS SyncFIFOTM 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
COMMERCIAL TEMPERATURE
SIGNAL DESCRIPTIONS
FIFO A and FIFO B are identical in every respect. The following description explains the interaction of input and output signals for FIFO A. The corresponding signal names for FIFO B are provided in parentheses.
Read Clock (RCLKA, RCLKB) -- Data can be read from Array A (B) on the the LOW-to-HIGH transition of RCLKA (RCLKB). The Empty Flag EFA (EFB) and Programmable Almost-Empty Flag PAEA (PAEB) are synchronized with respect to the LOW-to-HIGH transition of RCLKA (RCLKB). The write and read clock can be asynchronous or coincident. Read Enables (RENA1 RENA2 RENB1 RENB2 -- When RENA1, RENA2, RENB1, RENB2) both Read Enables RENA1, RENA2 (RENB1, RENB2) are LOW, data is read from Array A (B) to the output register on the LOW-to-HIGH transition of the read clock RCLKA (RCLKB). When either of the two Read Enable RENA1, RENA2 (RENB1, RENB2) associated with FIFO A (B) is HIGH, the output register holds the previous data and no new data is allowed to be loaded into the register. When all the data has been read from FIFO A (B), the Empty Flag EFA (EFB) will go LOW, inhibiting further read operations. Once a valid write operation has been accomplished, EFA (EFB) will go HIGH after tREF and a valid read can begin. The Read Enables RENA1, RENA2 (RENB1, RENB2) are ignored when FIFO A (B) is empty. Output Enable (OEA OEB -- When Output Enable OEA OEA, OEB) (OEB) is enabled (LOW), the parallel output buffers of FIFO A (B) receive data from their respective output register. When Output Enable OEA (OEB) is disabled (HIGH), the QA (QB) output data bus is in a high-impedance state. Write Enable 2/Load (WENA2/LDA WENB2/LDB -- This LDA, LDB) is a dual-purpose pin. FIFO A (B) is configured at Reset to have programmable flags or to have two write enables, which allows depth expansion. If WENA2/LDA (WENB2/LDB) is set HIGH at Reset RSA = LOW (RSB = LOW), this pin operates as a second write enable pin. If FIFO A (B) is configured to have two write enables, when Write Enable 1 WENA1 (WENB1) is LOW and WENA2/LDA (WENB2/LDB) is HIGH, data can be loaded into the input register and RAM array on the LOW-to-HIGH transition of every write clock WCLKA (WCLKB). Data is stored in the array sequentially and independently of any on-going read operation. In this configuration, when WENA1 (WENB1) is HIGH and/ or WENA2/LDA (WENB2/LDB) is LOW, the input register of Array A holds the previous data and no new data is allowed to be loaded into the register. To prevent data overflow, the Full Flag FFA (FFB) will go LOW, inhibiting further write operations. Upon the completion of a valid read cycle, FFA (FFB) will go HIGH after tWFF, allowing a valid write to begin. WENA1, (WENB1) and WENA2/ LDA (WENB2/LDB) are ignored when the FIFO is full. FIFO A (B) is configured to have programmable flags when the WENA2/LDA (WENB2/LDB) is set LOW at Reset RSA = LOW (RSB = LOW). Each FIFO contains four 8-bit offset registers which can be loaded with data on the inputs, or read on the outputs. See Figure 3 for details of the size of the registers and the default values.
INPUTS:
Data In (DA0 - DA8, DB0 - DB8) -- DA0 - DA8 are the nine data inputs for memory array A. DB0 - DB8 are the nine data inputs for memory array B.
CONTROLS:
Reset (RSA RSB -- Reset of FIFO A (B) is accomplished RSA, RSB) whenever RSA (RSB) input is taken to a LOW state. During reset, the internal read and write pointers associated with the FIFO are set to the first location. A reset is required after power-up before a write operation can take place. The Full Flag FFA (FFB) and Programmable Almost-Full Flag PAFA (PAFB) will be reset to HIGH after tRSF. The Empty Flag EFA (EFB) and Programmable Almost-Empty Flag PAEA (PAEB) will be reset to LOW after tRSF. During reset, the output register is initialized to all zeros and the offset registers are initialized to their default values. Write Clock (WCLKA, WCLKB) -- A write cycle to Array A (B) is initiated on the LOW-to-HIGH transition of WCLKA (WCLKB). Data set-up and hold times must be met with respect to the LOW-to-HIGH transition of WCLKA (WCLKB). The Full Flag FFA (FFB) and Programmable Almost-Full Flag PAFA (PAFB) are synchronized with respect to the LOW-toHIGH transition of the write clock WCLKA (WCLKB). The write and read clocks can be asynchronous or coincident. Write Enable 1 (WENA1 WENB1 -- If FIFO A (B) is conWENA1, WENB1) figured for programmable flags, WENA1 (WENB1) is the only enable control pin. In this configuration, when WENA1 (WENB1) is LOW, data can be loaded into the input register of RAM Array A (B) on the LOW-to-HIGH transition of every write clock WCLKA (WCLKB). Data is stored in Array A (B) sequentially and independently of any on-going read operation. In this configuration, when WENA1 (WENB1) is HIGH, the input register holds the previous data and no new data is allowed to be loaded into the register. If the FIFO is configured to have two write enables, which allows for depth expansion. See Write Enable 2 paragraph below for operation in this configuration. To prevent data overflow, FFA (FFB) will go LOW, inhibiting further write operations. Upon the completion of a valid read cycle, the FFA (FFB) will go HIGH after tWFF, allowing a valid write to begin. WENA1 (WENB1) is ignored when FIFO A (B) is full.
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72801/72811/72821/72831/72841 DUAL CMOS SyncFIFOTM 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
COMMERCIAL TEMPERATURE
LDA WENA1 LDB WENB1
0 0
WCLKA(1) WCLKB(1)
OPERATION ON FIFO A OPERATION ON FIFO B Empty Offset (LSB) Empty Offset (MSB) Full Offset (LSB) Full Offset (MSB)
0 1 1
1 0 1
No Operation Write Into FIFO No Operation
NOTE: 3034 drw 04 1. The same selection sequence applies to reading from the registers. RENA1 and RENA2 (RENB1 and RENB2) are enabled and read is performed on the LOW-to-HIGH transition of RCLKA (RCLKB). Figure 2. Writing to Offset Registers for FIFOs A and B
If FIFO A (B) is configured to have programmable flags, when the WENA1 (WENB1) and WENA2/LDA (WENB2/LDB)
are set LOW, data on the DA (DB) inputs are written into the Empty (Least Significant Bit) offset register on the first LOWto-HIGH transition of the WCLKA (WCLKB). Data are written into the Empty (Most Significant Bit) offset register on the second LOW-to-HIGH transition of WCLKA (WCLKB), into the Full (Least Significant Bit) offset register on the third transition, and into the Full (Most Significant Bit) offset register on the fourth transition. The fifth transition of WCLKA (WCLKB) again writes to the Empty (Least Significant Bit) offset register. However, writing all offset registers does not have to occur at one time. One or two offset registers can be written and then by bringing LDA (LDB) HIGH, FIFO A (B) is returned to normal read/write operation. When LDA (LDB) is set LOW, and WENA1 (WENB1) is LOW, the next offset register in sequence is written. The contents of the offset registers can be read on the QA (QB) outputs when WENA2/LDA (WENB2/LDB) is set LOW and both Read Enables RENA1, RENA2 (RENB1, RENB2) are set LOW. Data can be read on the LOW-to-HIGH transition of the read clock RCLKA (RCLKB). A read and write should not be performed simultaneously to the offset registers.
72801 - 256 x 9 x 2 8 7 Empty Offset (LSB) Reg. Default Value 007H 8 0 8 0 8 7
72811 - 512 x 9 x 2 0 Empty Offset (LSB) Default Value 007H 1 (MSB) 0 0 8 8 7
72821 - 1024 x 9 x 2 0 Empty Offset (LSB) Reg. Default Value 007H 1 (MSB) 00 0 8 7 Full Offset (LSB) Reg. Default Value 007H 0 (MSB) 0 8 1 (MSB) 00 0 0 0
8
7 Full Offset (LSB) Reg. Default Value 007H
0
8
7 Full Offset (LSB) Default Value 007H
8
0
8
1
72831 - 2048 x 9 x 2 8 7 Empty Offset (LSB) Reg. Default Value 007H 8 2 (MSB) 000 8 7 Full Offset (LSB) Reg. Default Value 007H 8 2 (MSB) 000 0 8 0 8 7 0 8 0 8 7
72841 - 4096 x 9 x 2 0 Empty Offset (LSB) Default Value 007H 3 (MSB) 0000 0 Full Offset (LSB) Default Value 007H 3 (MSB) 0000
3034 drw 05
0
0
Figure 3. Offset Register Formats and Default Values for the A and B FIFOs
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72801/72811/72821/72831/72841 DUAL CMOS SyncFIFOTM 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
COMMERCIAL TEMPERATURE
OUTPUTS:
Full Flag (FFA FFB -- FFA (FFB) will go LOW, inhibiting FFA, FFB) further write operations, when Array A (B) is full. If no reads are performed after reset, FFA (FFB) will go LOW after 256 writes to the 72801's FIFO A (B), 512 writes to the 72811's FIFO A (B), 1024 writes to the 72821's FIFO A (B), 2048 writes to the 72831's FIFO A (B), or 4096 writes to the 72841's FIFO A (B). FFA (FFB) is synchronized with respect to the LOW-toHIGH transition of the write clock WCLKA (WCLKB). Empty Flag (EFA EFB -- EFA (EFB) will go LOW, EFA, EFB) inhibiting further read operations, when the read pointer is equal to the write pointer, indicating that Array A (B) is empty. EFA (EFB) is synchronized with respect to the LOW-toHIGH transition of the read clock RCLKA (RCLKB). Programmable Almost-Full Flag (PAFA PAFB -- PAFA PAFA, PAFB) (PAFB) will go LOW when the amount of data in Array A (B) reaches the Almost-Full condition. If no reads are performed after reset, PAFA (PAFB) will go LOW after (256-m) writes to the 72801's FIFO A (B), (512-m) writes to the 72811's FIFO A (B), (1024-m) writes to the 72821's FIFO A (B), (2048-m)
writes to the 72831's FIFO A (B), or (4096-m) writes to the 72841's FIFO A (B). FFA (FFB) is synchronized with respect to the LOW-toHIGH transition of the write clock WCLKA (WCLKB). The offset "m" is defined in the Full Offset Registers. If there is no Full offset specified, PAFA (PAFB) will go LOW at Full-7 words. PAFA (PAFB) is synchronized with respect to the LOW-toHIGH transition of the write clock WCLKA (WCLKB). Programmable Almost-Empty Flag (PAEA PAEB -- PAEA, PAEB) PAEA (PAEB) will go LOW when the read pointer is "n+1" locations less than the write pointer. The offset "n" is defined in the Empty Offset Registers. If no reads are performed after reset, PAEA (PAEB) will go HIGH after "n+1" writes to FIFO A (B). If there is no Empty offset specified, PAEA (PAEB) will go LOW at Empty+7 words. PAEA (PAEB) is synchronized with respect to the LOW-toHIGH transition of the read clock RCLKA (RCLKB). Data Outputs (QA0 - QA8, QB0 - QB8 ) -- QA0 - QA8 are the nine data outputs for memory array A, QB0 - QB8 are the nine data outputs for memory array B.
TABLE 1: STATUS FLAGS FOR A AND B FIFOS
NUMBER OF WORDS IN ARRAY A NUMBER OF WORDS IN ARRAY B 72801 0 1 to n(1) to 255 (n+1) to (256-(m+1)) (256-m)(2) 256 72811 0 1 to n(1) to 511 (n+1) to (512-(m+1)) (512-m)(2) 512 72821 0 1 to n(1) to 1023 (n+1) to (1024-(m+1)) (1024-m)(2) 1024 H H H H L H H H L L L L H H H L H H H H
FFA FFB
PAFA PAFB
PAEA PAEB
EFA EFB
NUMBER OF WORDS IN ARRAY A NUMBER OF WORDS IN ARRAY B 72831 0 1 to n(1) (n+1) to (2048-(m+1)) (2048-m)(2) to 2047 2048
NOTES: 1. n = Empty Offset (n = 7 default value) 2. m = Full Offset (m = 7 default value)
FFA FFB
72841 0 H H H H L
PAFA PAFB
H H H L L
PAEA PAEB
L L H H H
EFA EFB
L H H H H
3034 tbl 09
1 to n(1) (n+1) to (4096-(m+1)) (4096-m)(2) to 4095 4096
5.15
8
72801/72811/72821/72831/72841 DUAL CMOS SyncFIFOTM 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
COMMERCIAL TEMPERATURE
tRS
RSA (RSB)
tRSS (RENB1, RENB2) tRSS (WENB1) tRSS WENA2/LDA (1) (WENB2/LDB) tRSF (EFB, PAEB) tRSF (FFA, PAFA) tRSF QA0 - QA8 (QB0 - QB8) tRSR tRSR tRSR
RENA1, RENA2
WENA1
EFA, PAEA
FFA, PAFA
OEA (OEB) = 1(2) OEA (OEB) = 0
3034 drw 06
NOTES: 1. Holding WENA2/LDA (WENB2/LDB) HIGH during reset will make the pin act as a second write enable pin. Holding WEN2/LDA (WENB2/LDB) LOW during reset will make the pin act as a load enable for the programmable flag offset registers. 2. After reset, QA0 - QA8 (QB0 - QB8) will be LOW if OEA (OEB) = 0 and tri-state if OEA (OEB) = 1. 3. The clocks RCLKA, WCLKA (RCLKB, WCLKB) can be free-running during reset. Figure 4. Reset Timing
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72801/72811/72821/72831/72841 DUAL CMOS SyncFIFOTM 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
COMMERCIAL TEMPERATURE
tCLK tCLKH WCLKA (WCLKB) tDH tDS (DA0 - DA8 DB0 - DB8) DATA IN VALID tENS tENH NO OPERATION tCLKL
(WENB1)
WENA1
WENA2 (WENB2) (If Applicable) tWFF tWFF
NO OPERATION
(FFB) tSKEW1(1) RCLKA (RCLKB)
FFA
(RENB1, RENB2)
RENA1, RENA2
3034 drw 07
NOTE: 1. tSKEW1 is the minimum time between a rising RCLKA (RCLKB) edge and a rising WCLKA (WCLKB) edge for FFA (FFB) to change during the current clock cycle. If the time between the rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than tSKEW1, then FFA (FFB) may not change state until the next WCLKA (WCLKB) edge. Figure 5. Write Cycle Timing
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10
72801/72811/72821/72831/72841 DUAL CMOS SyncFIFOTM 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
COMMERCIAL TEMPERATURE
tCLK tCLKH RCLKA (RCLKB) tENH (RENB1, RENB2) tREF tCLKL
RENA1, RENA2
tENS NO OPERATION tREF
EFA (EFB)
tA QA0 - QA8 (QB0 - QB8) tOLZ tOHZ tOE VALID DATA
OEA (OEB)
tSKEW1(1) WCLKA, WCLKB
WENA1 (WENB1)
WENA2 (WENB2)
3034 drw 08
NOTE: 1. tSKEW1 is the minimum time between a rising WCLKA (WCLKB) edge and a rising RCLKA (RCLKB) edge for EFA (EFB) to change during the current clock cycle. If the time between the rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than tSKEW1, then EFA (EFB) may not change state until the next RCLKA (RCLKB) edge. Figure 6. Read Cycle Timing
5.15
11
72801/72811/72821/72831/72841 DUAL CMOS SyncFIFOTM 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
COMMERCIAL TEMPERATURE
WCLKA (WCLKB) tDS DA0 - DA8 (DB0 - DB8) D0 (First Valid
D1
D2
D3
(WENB1)
WENA1
tENS
WENA2 (WENB2) (If Applicable) tFRL(1) tSKEW1 RCLKA (RCLKB) tREF
EFA (EFB)
(RENB1, RENB2)
RENA1, RENA2
tA QA0 - QA8 (QB0 - QB8) tOLZ tOE D0 tA D1
OEA (OEB)
3034 drw 09
NOTE: 1. When tSKEW1 minimum specification, tFRL = tCLK + tSKEW1 When tSKEW1 < minimum specification, tFRL = 2tCLK + tSKEW1 or tCLK + tSKEW1 The Latency Timings apply only at the Empty Boundary (EFA, EFB = LOW). Figure 7. First Data Word Latency Timing
5.15
12
72801/72811/72821/72831/72841 DUAL CMOS SyncFIFOTM 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
COMMERCIAL TEMPERATURE
NO WRITE WCLKA (WCLKB) tSKEW1 DA0 - DA8 (DB0 - DB8) tWFF tWFF tDS
NO WRITE
tSKEW1
tDS DATA WRITE
tWFF
FFA (FFB)
(WENB1)
WENA1
WENA2 (WENB2) (If Applicable)
RCLKA (RCLKB) tENS tENH tENS tENH
(RENB2)
RENA1
tA
(OEB)
OEA
LOW
tA QA0 - QA8 (QB0 - QB8) DATA IN OUTPUT REGISTER DATA READ NEXT DATA READ
3034 drw 10
Figure 8. Full Flag Timing
5.15
13
72801/72811/72821/72831/72841 DUAL CMOS SyncFIFOTM 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
COMMERCIAL TEMPERATURE
WCLKA (WCLKB) tDS tDS
DA0 - DA8 (DB0 - DB8) tENS
DATA WRITE 1 tENH tENS
DATA WRITE 2 tENH
WENA1, (WENB1)
tENS WENA2 (WENB2) (If Applicable) tFRL tSKEW1 RCLKA (RLCKB) tREF tREF tREF
(1)
tENH
tENS
tENH
tFFL tSKEW1
(1)
EFA (EFB)
(RENB1, RENB2)
RENA1, RENA2
OEA (OEB)
QA0 - QA8 (QB0 - QB8)
LOW tA
DATA IN OUTPUT REGISTER
DATA READ
3034 drw 11
NOTE: 1. When tSKEW1 minimum specification, tFRL maximum = tCLK + tSKEW1 When tSKEW1 < minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK + tSKEW1 The Latency Timings apply only at at the Empty Boundary (EFA, EFB = LOW). Figure 9. Empty Flag Timing
5.15
14
72801/72811/72821/72831/72841 DUAL CMOS SyncFIFOTM 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
COMMERCIAL TEMPERATURE
tCLKH WCLKA (WCLKB)
tCLKL
(4)
tENS (WENB1 tENS WENA2 (WENB2) (If Applicable)
tENH
WENA1
tENH
tPAF
(1)
(PAFB)
PAFA
Full - (m+1) words in FIFO
Full - m words in FIFO tSKEW2
(2)
(3)
tPAF
RCLKA (RCLKB)
RENA1, RENA2 (RENB1, RENB2)
tENS tENH
3034 drw 12
Notes: 1. PAF offset = m. 2. (256-m) words for the 72801, (512-m) words the 72811, (1024-m) words for the 72821, (2048-m) words for the 72831, or (4096-m) words for the 72841. 3. tSKEW2 is the minimum time between a rising RCLKA (RCLKB) edge and a rising WCLKA (WCLKB) edge for PAFA (PAFB) to change during that clock cycle. If the time between the rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than tSKEW2, then PAFA (PAFB) may not change state until the next WCLKA (WCLKB) rising edge. 4. If a write is performed on this rising edge of the write clock, there will be Full - (m-1) words in FIFO A (B) when PAFA (PAFB) goes LOW. Figure 10. Programmable Full Flag Timing
5.15
15
72801/72811/72821/72831/72841 DUAL CMOS SyncFIFOTM 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
COMMERCIAL TEMPERATURE
tCLKH WCLKA (WCLKB)
tCLKL
tENS (WENB1) tENS WENA2 (WENB2) (If Applicable)
tENH
WENA1
tENH
(1)
PAEA, PAEB
n words in FIFO tSKEW2(2) tPAE
n+1 words in FIFO tPAE
(3)
RCLKA (RCLKB) tENS tENH
RENA1, RENA2 (RENB1, RENB2)
3034 drw 13
NOTES: 1. PAE offset = n. 2. tSKEW2 is the minimum time between a rising WCLKA (WCLKB) edge and a rising RCLKA (RCLKB) edge for PAEA (PAEB) to change during that clock cycle. If the time between the rising edge of WCLKA (WCLKB) and the rising edge of RCLKA (RCLKB) is less than tSKEW2, then PAEA (PAEB) may not change state until the next RCLKA (RCLKB) rising edge. 3. If a read is performed on this rising edge of the read clock, there will be Empty + (n-1) words in FIFO A (B) when PAEA (PAEB) goes LOW. Figure 11. Programmable Empty Flag Timing
5.15
16
72801/72811/72821/72831/72841 DUAL CMOS SyncFIFOTM 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
COMMERCIAL TEMPERATURE
tCLK tCLKH WCLKA (WCLKB) tENH tCLKL
tENS
LDA (LDB)
tENS
WENA1
(WENB1) tDS
tDH
DA0 - DA7 (DB0 - DB7) PAE OFFSET (LSB) PAE OFFSET (MSB) PAF OFFSET (LSB) PAF OFFSET (MSB)
3034 drw 14
Figure 12. Write Offset Register Timing
tCLK tCLKH RCLKA (RCLKB) tENS tENH tCLKL
LDA (LDB)
tENS (RENB1, RENB2) tA QA0 - QA7 (QB0 - QB7) DATA IN OUTPUT REGISTER EMPTY OFFSET (LSB) EMPTY OFFSET (MSB) FULL OFFSET (LSB) FULL OFFSET (MSB)
3034 drw 15
RENA1, RENA2
Figure 13. Read Offset Register Timing
5.15
17
72801/72811/72821/72831/72841 DUAL CMOS SyncFIFOTM 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
COMMERCIAL TEMPERATURE
OPERATING CONFIGURATIONS
SINGLE DEVICE CONFIGURATION -- When FIFO A (B) is in a Single Device Configuration, the Read Enable 2 RENA2 (RENB2) control input can be grounded (see Figure 14). In
this configuration, the Write Enable 2/Load WENA2/LDA (WENB2/LDB) pin is set LOW at Reset so that the pin operates as a control to load and read the programmable flag offsets.
RSA (RSB)
WCLKA (WCLKB) RCLKA (RCLKB) IDT 72801 72811 72821 72831 72841 FIFO A (B)
WENA1 (WENB1)
WENA2/LDA (WENB2/LDB) DA0 - DA8 (DB0 - DB8)
RENA1 (RENB1) OEA (OEB)
QA0 - QA8 (QB0 - QB8)
FFA (FFB) PAFA (PAFB)
EFA (EFB) PAEA (PAEB)
RENA2 (RENB2)
Figure 14. Block Diagram of One of the 72801/72811/72821/72831/72841's two FIFOs configured as a single device
3034 drw 16
WIDTH EXPANSION CONFIGURATION -- Word width may be increased simply by connecting the corresponding input control signals of FIFOs A and B. A composite flag should be created for each of the end-point status flags EFA and EFB, also FFA and FFB). The partial status flags PAEA, PAFB, PAEA and PAFB can be detected from any one device. Figure 15 demonstrates an 18-bit word width using the two FIFOs contained in one IDT72801/72811/72821/72831/72841. Any word width can be attained by adding additional IDT2801/
9
72811/72821/72831/72841s. When the IDT2801/72811/72821/72831/72841 is in a Width Expansion Configuration, the Read Enable 2 (RENA2 and RENB2) control inputs can be grounded (see Figure 15). In this configuration, the Write Enable 2/Load (WENA2/LDA, WENB2/LDB) pins are set LOW at Reset so that the pin operates as a control to load and read the programmable flag offsets.
*
RESET
RSA
DATA IN WRITE CLOCK WRITE ENABLE WRITE ENABLE/LOAD FULL FLAG 18
DB0 - DB8
RSB
RAM ARRAY B
*
9
DA0 - DA8 WCLKA
RAM ARRAY RCLKA A WCLKB
EFA EFB
RCLKB
EMPTY FLAG READ CLOCK READ ENABLE OUTPUT ENABLE
WENA1
WENA2/LDA
FFA FFB
256x9 WENB1 256x9 512x9 OEA1 512x9 1024x9 2WENB2/LDB 1024x9 2048x9 2048x9 4096x9 4096x9
RENA1
RENB1 OEB
QB0 - QB8 9
*
18
DATA OUT
RENA2
QA0 - QA8
RENB2
3034 drw 17
9
Figure 15. Block diagram of the two FIFOs contained in one 72801/72811/72821/72831/72841configured for an 18-bit width-expansion
5.15
18
72801/72811/72821/72831/72841 DUAL CMOS SyncFIFOTM 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
COMMERCIAL TEMPERATURE
TWO PRIORITY DATA BUFFER CONFIGURATION The two FIFOs contained in the IDT2801/72811/72821/ 72831/72841 can be used to prioritize two different types of data shared on a system bus. When writing from the bus to the FIFO, control logic sorts the intermixed data according to
type, sending one kind to FIFO A and the other kind to FIFO B. Then, at the outputs, each data type is transferred to its appropriate destination. Additional IDT2801/72811/72821/ 72831/72841s permit more than two priority levels. Priority buffering is particularly useful in network applications.
9
WENA1
OEA RENA
Control Logic
RAM ARRAY A RCLKA WCLKA
Image Processing Card Clock Address Control I/O Data
Processor Clock Address Control Data
9
VCC
DA0-DA8 QA0-QA8 WENA2 RENA2 IDT 72801 72811 72821 72831 72841 RAM ARRAY B WCLKB RCLKB
9
Data
Control Logic
9-bit bus
Voice Processing Card Clock
Control Logic
RAM
9
WENB1
DB0-DB8
9
OEB2 RENB1
QB0-QB8
Address Control I/O Data
WENB2
RENB2
Data
9
VCC
3034 drw 18
Figure 16. Block Diagram of Two Priority Configuration
5.15
19
72801/72811/72821/72831/72841 DUAL CMOS SyncFIFOTM 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
COMMERCIAL TEMPERATURE
BIDIRIECTIONAL CONFIGURATION The two FIFOs of the IDT2801/72811/72821/72831/72841 can be used to buffer data flow in two directions. In the
example that follows, a processor can write data to a peripheral controller via FIFO A, and, in turn, the peripheral controller can write the processor via FIFO B.
VCC
RAM ARRAY A WENA2 RENA2 WCLKA RCLKA
WENA1
Processor Clock Control Logic Address Control Data
9 9
DA0-DA8 QA0-QA8 IDT 72801 72811 72821 72831 72841
OEA RENA1
9
Peripheral Controller DMA Clock Control Logic Address Control I/O Data Data
9
9-bit bus
RAM ARRAY B RCLKB
RAM
9
WENB1 RENB1 OEB WCLKB
QB0-QB8 DB0-DB8 RENB2 WENB2
9
3034 drw 19
9
VCC
Figure 17. Block Diagram of Bidirectional Configuration
5.15
9-bit bus
20
72801/72811/72821/72831/72841 DUAL CMOS SyncFIFOTM 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
COMMERCIAL TEMPERATURE
DEPTH EXPANSION -- IDT2801/72811/72821/72831/ 72841 can be adapted to applications that require greater than 256/512/1024/2048/4096 words. The existence of double enable pins on the read and write ports allow depth expansion. The Write Enable 2/Load (WENA2, WENB2) pins are used as a second write enables in a depth expansion configuration, thus the Programmable flags are set to the default values. Depth expansion is possible by using one enable input for system control while the other enable input is controlled by expansion logic to direct the flow of data. A typical application
would have the expansion logic alternate data access from one device to the next in a sequential manner. The IDT2801/ 72811/72821/72831/72841 operates in the Depth Expansion configuration when the following conditions are met: 1. WENA2/LDA and WENB2/LDB pins are held HIGH during Reset so that these pins operate as second Write Enables. 2. External logic is used to control the flow of data. Please see the Application Note" DEPTH EXPANSION OF IDT'S SYNCHRONOUS FIFOs USING THE RING COUNTER APPROACH" for details of this configuration.
ORDERING INFORMATION
IDT XXXXX Device Type L Power XX Speed PF Package Process/ Temperature Range
BLANK Commercial (0C to +70C)
Thin Quad Flat Pack (TQFP)
12 15 20 25 35
Clock Cycle Time(tCLK), speed in Nanoseconds
Low Power
72801 72811 72821 72831 72841
256 x 9 DUAL FIFO 512 x 9 DUAL FIFO 1024 x 9 DUAL FIFO 2048 x 9 DUAL FIFO 4096 x 9 DUAL FIFO
3034 drw 20
5.15
21

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